1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a complementary metal oxide semiconductor (CMOS, broadly, CMIS ) device used in an output circuit of a simiconductor integrated cirucit (IC).
2. Description of the Related Art
In semiconductor IC's, a prior art output circuit uses an inverter or a source follower cirucit having an active load. In this prior art output circuit, however, a current steadily flows, which thereby increases the power consumption. Also, the driving power is low due to the limitation of a current flowing through the active load.
In order to reduce the power consumption as well as enhance the driving power, CMOS source follower circuits have been used in output circuits of semiconductor IC's.
A prior art CMOS source follower circuit is comprised of a semiconductor substrate partitioned by a P-type region and a N-type region. Formed in the P-type region are N-type regions as source and a drain for an N-channel enhancement-type transistor. Also, formed in the P-type region are N-type regions as a source and a drain for an N-channel enhancement-type transistor. The drain of the N-channel transistor is connected to a power supply terminal V.sub.DD having a voltage of +10 V, for example, and the drain of the P-channel transistor is connected to a power supply terminal V.sub.SS whose voltage, for example -10 V, is lower than that of the terminal V.sub.DD. Also, gate electrodes of the N-channel transistor and the P-channel transistor are connected commonly to an input node. Further, the sources of the N-chapel transistor and the P-channel transistor are connected commonly to an output node.
Also, the channel of the N-channel transistor is connected to the power supply terminal V.sub.SS, i.e., the back bias voltage of the N-channel transistor is V.sub.SS. 0n the other hand, the channel of the P-channel transistor is connected to the output node, i.e., the back bias voltage of the P-channel transistor is a voltage at the output node. This will be explained later in detail.
In the above-mentioned prior art CMOS source follower circuit, however, when the voltage at the input node is positively large, the threshold voltage of the N-channel transistor is enlarged due to the fact that the channel (back bias) voltage of the N-channel transistor is fixed at V.sub.SS, and the source voltage of the N-channel transistor is increased with respect to the back bias voltage V.sub.SS. As a result, the gain of the CMOS source follower circuit is reduced in the case where the voltage at the input node is large.
Also, in the input/output characteristics of the above-mentioned prior art CMOS source follower circuit, there is a dead gap voltage region where the voltage at the output node is zero when the voltage at the input node is within a range, so that the distortion of the input/output characteristics is large.